When communicating data in a bus system working with a source synchronous clock, a module, which in the sending mode outputs not only data to the data bus, also applies a source clock signal generated by it to a source clock line provided specifically for this purpose, whereby a fixed predefined time spacing is maintained between the data and the source clock signal. This time spacing is needed to ensure correct data acceptance in the receiving module in being controlled by the source clock signal. On receiving the data in the receiving module, its receiver assemblies attain a stable status before the source clock signal triggers acceptance of the data value in each case. This waiting time until the stable status is attained, following application of the data signal, is also termed the setup time in trade literature. The time spacing between the sent data and the source clock signal needs to be dimensioned so that the source clock signal in no event triggers data acceptance in the receiving module before timeout of the setup time of the receiver assemblies in each case. This time spacing to be maintained thus limits the maximum data transfer rate in the bus system. Even when modules are used in the bus system whose receiver assemblies have a shortened setup time, the system cannot work at a higher transfer rate since the time spacing between the data and the source clock signal cannot be varied.